Higher functions and integration of semiconductor integrated circuits (LSI) are being achieved. Conventionally, this has resulted in excessive power consumption and an IR drop during the LSI operation.
In other words, a major cause of excessive power consumption and IR drop during an LSI operation is that clock signals are fed into many flip-flops (FF) provided in a circuit substantially simultaneously and thereby the FFs operate substantially simultaneously.
Conventionally, in LSI designing, the number of FFs that operate substantially simultaneously is limited by using a clock gating circuit (CGC: Clock Gating Circuit) that achieves a clock gating technique.
A circuit operation during a test may be very different from that of a normal operation, thus the power consumption and the IR drop may be much different, i.e., much larger than expected during the designing, and this may be a cause for an error.
Conventionally, LSIs have been provided that may reduce power consumption using the clock signal gating technique, however, the technique that is applied during a normal operation may not be effective during a test operation. Accordingly, excessive power consumption and an IR drop may result.
Conventionally, various methods have been proposed for testing a semiconductor integrated circuit to which a clock signal gating technique is applied.